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08_4_hdmi_loop
说明: HDMI做为视频输出输入接口已经广泛使用很长时间,主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验,来练习视频的时序和视频颜色的表示,为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)
- 2020-06-17 09:00:02下载
- 积分:1
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gg
说明: FPGA实现基带成型滤波器,升余弦滚降系数,多进制调制(FPGA)
- 2010-12-20 17:55:18下载
- 积分:1
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固定的点复杂 FFT
固定的 128 点复杂 FFT
或
64/8/16 点
- 2022-02-06 02:51:48下载
- 积分:1
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用VHDL的VGA控制
VHDL控制VGA 在显示器上显示图形,分辨率800X600,晶振50Mhz-VGA control with VHDL
- 2022-01-25 17:41:08下载
- 积分:1
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xapp774
基于tus5000评估板的VHDL源代码,用于超声波检测,xinlinx提供的(Based on the VHDL source code tus5000 uation board, used in ultrasonic testing, xinlinx provide)
- 2021-02-07 11:39:55下载
- 积分:1
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nan
液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)
- 2012-04-28 15:57:46下载
- 积分:1
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四位静态数码管控制器,含详细的中文注释,VERILOT源码....
四位静态数码管控制器,含详细的中文注释,VERILOT源码.-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.
- 2022-03-29 22:12:43下载
- 积分:1
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verilog-code-style-specification
企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)
- 2015-05-31 16:06:37下载
- 积分:1
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Convolutional code encoder and Viterbi decoding to achieve
卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
- 2022-01-28 03:11:57下载
- 积分:1
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用VHDL语言编写的一个16分频器,也在修订过程中任意2…
利用VHDL语言编写的一个16分频器,另外可以在程序中修改为任意2N的分频器-use VHDL prepared a 16 dividers, Also in the revision process to be arbitrary 2 N Divider
- 2023-05-20 12:30:04下载
- 积分:1