VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的....

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第二个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The second document

Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)

32-bit shifter, shifter, 32-bit.Very goog as a study file.

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)

tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)

vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2

timblogiw.c timberdale FPGA LogiWin Video In driver.

GPU编程的经典之作,值得一读。 GPU运算效率比CPU高出一截，学习GPU编程会大有裨益(a book for GPU_Programming)

基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)