dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源...

此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx

Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

基于PCI总线和LPC接口的POST主板诊断卡代码，已经通过fpga测试可以使用，性能非常稳定。(Based on the PCI bus and LPC POST motherboard diagnostic card code to interface fpga has passed the test can be used, the performance is very stable.)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

verilog学习资料。附带简单的源代码列子，可以直接使用和仿真。(verilog learning materials. Source code with a simple Lie Zi, and simulation can be used directly.)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

NN CONTROLLER FOR UPQC

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)