dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源...

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

FFT处理器的FPGA设计方法，适合做信号处理的技术人员参考，用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve

UML2 apprendre a modeliser a l aide de UML

说明：  IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)

一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)

本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA" s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.

用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures