VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础

本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)

manchester_verilog源代码(manchester_verilog source code)

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

ieee paper on power gating and can be use full for implementing on ip core

Verilog经典教程，非常好的资料！值得一看！(Classic Verilog tutorials, very good information! Worth a visit!)

非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog(very nice book for catabult study)

基于FPGA的ip核FIR低通滤波器，实现滤波功能，简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)

基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim