VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础

通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.

just division the clock into 2

说明：  一个交通灯设计,简单的实现，没有添加其他的显示管(Traffic Light System)

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

 交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；  当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；  clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；  输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。 ( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control  When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state  clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights  output terminal r, g, y represent the three colors of traffic lights bright, the off state.)

汉明码转换，在FPGA上用verilog实现(hamming encoder, using FPGA)

lehmer random number generator method to generate test patterns of circuit