VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础

内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)

说明：  基于HSPICE实现的反相器链，并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

program in hdl that this open mind in digital resources

verilog coding for butterworth filter with cut off frequency with 500hz

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

8051的verilog内核，fpga里实现8051的话用得上-8051 Verilog cores, fpga achieve useful 8051 words

un controller pi par le langage VHDL xilinx ise design 13.2

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)

sourceinsight的verilog插件-The Verilog sourceinsight plug-ins