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leading-zero
对于32位寄存器前导零个数的计数,一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分:1
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LM75A
FPGA读取LM75A温度数据,并在段码LED上实时显示。(The temperature data of LM75A are read by FPGA and displayed on segment code LED in real time)
- 2021-03-29 11:19:10下载
- 积分:1
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frequency-digital-phase-measuring-
低频数字式相位测量仪,数码管显示相位差,精度为0.1(Low frequency digital phase measuring instrument, digital pipe display phase difference
)
- 2011-08-10 00:45:49下载
- 积分:1
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vending-machine
用Verilog实现自动售货机功能,代码较初级。易懂,内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分:1
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Compteur_VHDL
VHDL code of a counter
Code VHDL d un compteur
- 2016-07-09 21:00:59下载
- 积分:1
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arm7
ARM7 VERILOG源码,非常精简,3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
- 2009-12-02 10:57:51下载
- 积分:1
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VHDL example, there are nearly a hundred examples, can be carried out in quartur...
VHDL实例,有近百个实例,都是可以在quarturs 上进行仿真的,大部分都可以通过,对初学者是一非常不错的-VHDL example, there are nearly a hundred examples, can be carried out in quarturs simulation, most of them can pass, for beginners is a very good
- 2022-04-16 23:40:20下载
- 积分:1
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VHDL电子抢答器的实现。有多个文件,主控件是用图行实现。其余各功能模块用VHDL实现...
VHDL电子抢答器的实现。有多个文件,主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
- 2022-03-14 00:36:42下载
- 积分:1
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ROM模块,功能在于,是创建一个简易的rom模块
ROM模块,功能在于,是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1