在EFF的代码地址异步FIFO的灰色代码详细设计…

说明：  URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

VHDL operators basics

verilog设计的32位IO口扫描后通过串口发送到计算机(Verilog design of 32 bit IO export after scanning through the serial port to the computer)

产生svpwm波形，可以参考下载,以便学习交流(gennerate SVPWM wave)

Rotary Encoder Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel. Events counter for the Rotary Encoder and displaying the events on the front panel Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).

fpga_sopc_enc28j60_tcp_ip_测试，源码程序包，本人测试通过！(Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!)

此代码是用于旋转一个步进电机所需的方向。

实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.

说明：  千年服务端修改工具，千年db数据在线修改(Millennium server modification tool Millennium server modification tool)