SPI串口的内核实现spicore SPI串口的内核实现spicore

verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)

一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)

实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL

ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)

电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.

1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT

VHDL常用源程序，希望以EDA技术学习者有用！-VHDL source code commonly used, I hope to EDA technology learners useful!