SPI串口的内核实现spicore SPI串口的内核实现spicore

Test for VHDL just a student version

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity song is    port(clk_4MHz,clk_4Hz:in std_logic;      ----预置计数器和乐谱产生器的时钟         digit:buffer std_logic_vector(6 downto 0);  ----高、中、低音数码管指示         zero:out std_logic_vector(4 downto 0);     ----用于数码管高位置低  

结合截图，quartus2与ModelSim的联调的详细操作步凑，使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly

实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)

该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )

说明：  Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)

verilog 入门概述 新手学习资料-Getting Started with an overview of novice learning materials verilog

fpga驱动TLC7528程序，相当好用，绝对能用(FPGA PROGRAM OF TLC7528)