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FPGA_Turbo
Turbo码编解码的FPGA实现,verilog语言编写(Implementation ofTurbo code on FPGA , using Verilog language)
- 2021-04-19 09:48:51下载
- 积分:1
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Cmos 全加法器使用绝热逻辑
绝热电路都是使用"可逆逻辑"的低功耗电路以节省能源。与传统的CMOS电路,在开关过程中消耗能量,不同绝热电路试图节约费用由以下两个关键的规则:
永远不会打开一个晶体管时电压源之间
- 2023-04-29 04:00:02下载
- 积分:1
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NIOS II IDE 编程, uart_txd测试程序,仅供参考。
NIOS II IDE 编程, uart_txd测试程序,仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.
- 2022-11-30 03:45:03下载
- 积分:1
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D触发器的基本功能的理解及应用,特别是记忆传输功能使用WAIT语句编写地理解...
D触发器的基本功能的理解及应用,特别是记忆传输功能使用WAIT语句编写地理解-D flip-flop understanding of the basic functions and applications, in particular the memory transfer function using the WAIT statement is prepared to understand
- 2022-01-26 05:04:12下载
- 积分:1
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ser_to_parr
很有用的10bit串并转换verilog程序,需要的可以拿去参考下,在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分:1
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PWM
verilogHDL语言编写,简单的FPGA脉冲程序,初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)
- 2012-12-27 11:54:45下载
- 积分:1
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codings
wavelet transform of a signal,it is important and useful code to trans form frequency to time domain
- 2013-11-10 15:10:32下载
- 积分:1
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usb_latest[1].tar
sub opercore USB CRC5 and CRC16 Modules ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)
- 2009-11-17 13:53:06下载
- 积分:1
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NN-using-FPGA
thesis about design and implementation neural network using FPGA
- 2013-12-29 16:23:52下载
- 积分:1
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Several common multiplier Verilog, VHDL code
几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
- 2022-03-12 09:47:07下载
- 积分:1