Several common multiplier Verilog, VHDL code

ＦＰＧＡ与ＳＤＲＡＭ　的　ＶＨＤＬ　接口设计(ｔｈｅ　interface of FPGA and SDRAM)

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

vendingmachine vhdl code

PLL中的TDC和DCO代码,是TI公司团队的，相当经典的代码，非常不错(the code of TDC and DCO)

xilinx的串口仿真程序-xilinx simulator programme of serial port

具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is

AHB to Wishbone memory interface VHDL source code

说明：  SDRAM硬件控制,fpga的verilog语言，适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)

wishbone接口的设计，在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested