Cmos 全加法器使用绝热逻辑

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

VHDL 快速参考手册，简要概括了VHDL，非常适合做开发参考-VHDL Quick Reference Guide, a brief summary of VHDL, is well suited to do the development of reference

Synopsys 8051 IP core documentation.

RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；(-RS Coding and Decoding Verilog code，　implement RS（544,514))

这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

模拟示波器的现实程序，有x，y和光标。采用AD5440输出，现实效果很好。（示波器x-y方式）(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))

说明：  DDS VHDL include everything of dds AD9914

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

tle转换为六根数的c++源代码，英文原版代码，测试可用(tle converted to six the number of c++ source code, the English original code, test available)