FPGA数字电子系统设计与开发实例导航的所有例程

给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现(Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone)

iic master 通过FPGA验证··成功对eeprom读写操作 clk_div：FPGA 板子分频时钟，满足SCL时钟线速度达400KB main_state.v：顶层状态机，控制master接口整个工作过程 scl_generator.v:master接口，有SCL状态机产生器和master接口状态机两部分组成 mainsmtb.v：在modelsim环境下的仿真激励 top.v设计顶层模块

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)

卷积码(2,1,7)编码器，一个输入，两个输出(Convolution code (2,1,7) encoder, an input and two outputs)

Verilog代码，支持IO，中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)