登录
首页 » VHDL » vhdl设计事例,有助于FPGA初学着,High

vhdl设计事例,有助于FPGA初学着,High

于 2023-06-12 发布 文件大小:650.89 kB
0 964
下载积分: 2 下载次数: 1

代码说明:

vhdl设计事例,有助于FPGA初学着,High-Performance 1024-Point Complex FFT-vhdl design examples, to help novice FPGA. High-Performance 1024-Point Complex FFT

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 使用vhdl语言编写的100个常用程序的例子
    使用vhdl语言编写的100个常用程序的例子-The use of VHDL language 100 examples of commonly used procedures
    2022-08-18 05:39:29下载
    积分:1
  • cmp
    VHDL code comparator
    2012-06-26 18:50:52下载
    积分:1
  • Poiseuille---BANFANTAN
    格子玻尔兹曼方法模拟poiseuille流,半反弹边界,适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)
    2021-04-07 13:29:01下载
    积分:1
  • 基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用
    基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using
    2023-06-18 04:20:03下载
    积分:1
  • VHDL-Handbook.pdf
    VHDL Handbook by HARDI Electronics AB
    2015-02-17 17:50:32下载
    积分:1
  • VHDL写的串口,很好用,程序非常简单,可以调试用
    VHDL写的串口,很好用,程序非常简单,可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
    2022-08-08 18:58:10下载
    积分:1
  • demo6-beep
    说明:  demo6 蜂鸣器实验 蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)
    2020-12-27 22:59:02下载
    积分:1
  • 内有LED译码器,汉明纠错译码器,地址译码器,最高优先译码器,双2-4译码器等VHDL的源代码...
    内有LED译码器,汉明纠错译码器,地址译码器,最高优先译码器,双2-4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
    2022-12-30 11:40:03下载
    积分:1
  • 红外
    说明:  一个红外遥控,可以学习其他的红外编码,并存储记忆,并且将学习到的编码发送(An infrared remote control)
    2020-06-25 10:27:32下载
    积分:1
  • Coding Files
    Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
    2017-12-13 23:58:23下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载