基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用

已经正式出版，西安电子科技大学出版社，FPGA设计及应用，作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)

能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)

用VHDL编写的huffman编码的源程序(With the VHDL source code written in huffman coding)

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

AHB to Wishbone memory interface VHDL source code

HDL example source code 2/5 dff_en

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

传感信号无线数字传输系统的设计与实现.kdh(err)