利 用 来 vhdl 设 计 p cm的 实 现

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer

在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)

设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源-Design and production of a 14-key electric piano tone into a number of music scores advance in 4Hz clock circuit under the control of automatic play through 220V power adapter to provide power to the circuit

在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)

FPGA做VGA通讯的详细资料，我找了很久才收集起的，很有用，可供初学者学习实用-FPGA to do VGA communication details, I am looking for a long time before starting the collection, very useful for beginners to learn practical

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)