利 用 来 vhdl 设 计 p cm的 实 现

SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

一些例子程序需要的话可以下来看看新手推荐-Some examples of procedures can be down if necessary to see novice Recommended

1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share

FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程(FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming)

dataflow muliplexer in FPGA

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

IIC主设备的代码实现（verilog),从设备模型-IIC main equipment of the code (verilog), from the device model

基于fpga和xinlinx ise的鼠标应用vhdl程序，希望对你有所帮助！-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL