用32位NiosII处理器实现RS232通信，可以给初学者一个借鉴。

Run-Length Encoder Example: Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07 Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07

基于VHDL语言开发的mcu与外部器件的接口程序，解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.

This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.

这本书介绍了数字应用的底层电路设计的理论及实验程序，非常有用，是一本很好的工具书。(This book describes the application of the underlying digital circuit design theory and experimental procedures, very useful, is a good tool.)

说明：  verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

DEBOUNCEfpga的实现，运用软件实现数码管的变化(fpga of the)