四路抢答器的设计与实现

巴克码装到信息内同时将巴克码识别出来，实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)

文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)

VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)

Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.

这份文献主要介绍了dsp builder 8.0的功能及使用手册，介绍了如何和matlab一起使用的步骤。(This literature focuses on the dsp builder 8.0 features and user manual describes how to matlab and used in conjunction with steps.)