一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Xilinx公司的ml505 FPGA上的位码文件和配置文件，可以直接下载使用！...

快速付里叶变换子程序所需 RAM 空间以输入的首地址为基址,向增加的方向扩展(Fast Fourier Transform subroutine RAM space required to input the first address of the site was to increase the direction of expansion)

说明：  一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

说明：  常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)

VHDL 快速参考手册，简要概括了VHDL，非常适合做开发参考-VHDL Quick Reference Guide, a brief summary of VHDL, is well suited to do the development of reference

来自于NIOSII的那些事，该书详细地介绍了NIOSS的使用过程，非常适合初学者。(From the NIOSII those things, the book are detailed in this paper NIOSS use process, very suitable for beginners. )

用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去-51 Singlechip c language keyboard scanning procedures for transplantation to other hardware up