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fir_filter
LOW pass FIR filter for multirate processing
- 2015-02-09 09:59:02下载
- 积分:1
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用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。...
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
- 2022-10-05 02:20:03下载
- 积分:1
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ethernet_tri_mode_rtl.tar
以太网控制器verilog,含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分:1
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DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式...
DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
- 2022-01-23 11:02:21下载
- 积分:1
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xspUSB
关于usb调试相关测试 代码,用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)
- 2020-06-22 23:00:01下载
- 积分:1
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SPI_Master
此代码是SPI接口的Master的Verilog源代码,经上板测试是没有问题的,请大家放心使用
(This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)
- 2021-02-25 09:19:38下载
- 积分:1
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waveform_-generator
简易信号波形发生器,可以产生四种波形,频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
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- 2011-06-12 21:13:27下载
- 积分:1
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SoftCore_LED80-master
说明: 使用VHDL实现的LED-80分组密钥,相对于其它密钥具有硬件实现面积更小的特点(vhd code of a lightweight block cipher LED-80)
- 2020-03-24 20:57:31下载
- 积分:1
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Verilog_traffic
若农场路无车辆,则在高速路保持绿灯。在探测农场路有车辆,高速路上的交通灯应由绿到黄,再到红,并允许农场路方向灯变绿,绿灯亮一段时间,由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)
- 2020-07-17 21:08:48下载
- 积分:1
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FpMultiplier
说明: 可调矩阵,最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)
- 2021-02-09 00:25:23下载
- 积分:1