一篇比较好的spi接口的vhdl实现的参考

Convolotional Decoding Based on Viterbi Algorithm

VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)

FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚 (Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)

I2C总线在可编程逻辑器件上实现的VHDL源码-VHDL source codes for realizing I2C

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动-VGA display interface Verilog control procedures. Control for VGA display driver