vhdl 中各种数据类型的转换实现,可以调用函数库实现

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

WCDMA数字频域干扰抵消器，绝对的高手写的文档和代码，里面资料齐全方便自学，是很好的学习FPGA实现无线通信模块的资料。(WCDMA Frequency Domain Interference Cancellation figures, the absolute master of written documentation and code, which complete information to facilitate self-learning, is a very good learning FPGA implementation of wireless communications and information.)

这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出，在接收端进行串行输入和并行输出的算法。

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)

串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)

基于FPGA的抢答器程序，VHDL 语言描述。(FPGA)

说明：  激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)

ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)