Study the performance of state machine. Rar inspect the performance of state mac...

FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理(FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing)

一个双向总线的vhdl实现-a two-way bus VHDL achieve

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .

verilog code for dma

说明：  FPGA测试程序，仅供测试硬件是否能够运行，主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)

verilog source code for SD card SLAVE DEVICE IP-Core

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.

华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.

应用背景在本文中，一个高性能和高度优化Rijndael AES算法的硬件实现了设计并实现Xilinx Virtex-5 xc5vlx50FPGA器件。设计采用模块化利用VHDL语言的方法。设计工作正确如图所示。这个所提出的设计的性能进行评估的基础上吞吐量和面积。我们的设计利用了速度339.087兆赫，这意味着吞吐量4.34用399片Virtex-5 FPGA面积Gbps。关键技术本文提出了一种有效的Rijndael算法的硬件实现高级加密标准（AES）加密算法采用最先进的现场可编程门阵列（FPGA）。在非常高速集成电路设计的设计硬件描述语言（VHDL）。时序仿真进行验证所设计的电路的功能。性能评估也做了吞吐量和区域。在国家的最先进的Xilinx Virtex-5实现设计（xc5vlx50ffg676-3）FPGA实现吞吐量4.34千兆位/秒，总共使用了399片。