Can be directly downloaded to the chip used in the complete UART with FIFO proce...

  该代码主要是针对TCD1500c 的时序图，用verilog 语言实现的TCD1500c的时序图，利用modelsim 进行仿真，并且通过测试。

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

verilog基础练习，介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation

一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated

说明：  verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)

it shows bcd counter

Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

运用VHDL语言编写的检测1111的序列检测代码和加法器，运用verlog语言的交通灯，流水灯，出租车自动计费器等