Can be directly downloaded to the chip used in the complete UART with FIFO proce...

Ethernet MAC-MII interface of Transmit

采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.-Using Verilog HDL language hardware design, the realization of the basic public telephone billing function, design integrity.

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

利用康芯公司的FPGA芯片设计制作频率计，实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)

很好的tft参考实列，通用的8位并口，非常快移值-Tft good reference is listed, eight general-purpose parallel port, very fast shift value

说明：  基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)