UDP协议的Verilog代码

说明：  基于FIR设计的100阶数字滤波器，选择的矩形窗(100 - order digital filter based on FIR)

基于verilog的AMI协议编码, 已用modelsim验证。

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

关于VHDL和verilog的数码管显示程序，写的很好，值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)

这也是VHDL语言编写的一个小程序，对于VHDL入门很有帮助~~(This is a small program VHDL language, VHDL entry-helpful ~ ~)

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and CRC7 for command line Wishbine 总线使用。完整的SD卡控制器，支持文件系统，高速传输。

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )

此代码是Turbo码译码算法中的Max-Log-MAP译码算法。