UDP协议的Verilog代码

用verilog状态机实现的自动售货机，是一次课程作业，参考了网上的例子进行了修改(Automatic vending machine implemented with Verilog state machine)

FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)

基于fpga的coms摄像头 扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

1、掌握WALSH码产生的原理和WALSH码的特性。 2、掌握WALSH码的产生和特性分析的软件仿真。 3、掌握WALSH码的硬件产生方法。 (1, master code WALSH WALSH code generation principles and characteristics. 2, master WALSH code generation and characterization of the software simulation. 3, master code WALSH hardware generation approach.)

QuartusII多路选择器,数字电路环境，大三EDA技术实验(Quartus,chosen conductos in matheathics field)

部分组合逻辑数字电路的VHDL代码，包含必要的功能描述(Some combinational logic digital circuits VHDL code, containing the necessary functional description)

mipi转LVDS接口， verilog代码，在lattice 芯片上使用，已验证(MIPI to LVDS interface)