基于FPGA的Turbo译码算法的实现

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

ps2 mouse controller

Verilog RS232代码， 分为三个模块，时钟产生模块，发送数据模块，接收数据模块。 整个工程的功能是，你从串口上位机发送什么数据，串口就将该数据重新发送回上位机

说明：  网口UDP的FPGA仿真代码，经过测试能够实现预想功能(etherneit udp verilog fpga code)

将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)

说明：  之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

altera mvb fpga sopc 设计参考文档，有一定价值(mvb fpga sopc Design scheme)

应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used to set the register address pointer, and write the register data. I2C reads are used to read the register data. Successive data reads or writes result in data being read or written from incremental register addresses. There is no limit on how much data can be read or written in a single access, but the internal register address pointer will wrap round to 0 once it reaches 255. Note that the address pointer is not initialized at reset, and the address pointer must