完整SD控制器！支持文件系统。

说明：  SDRAM控制，通过VHDL语言编写可运行至133MHz。(SDRAM control, written in VHDL language, can run to 133MHz.)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

n_bit_paralleLoadShiftRegJK

uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)

Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

xilink DPD V6.0 IP Core design example

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

fpga的一些经验之谈，对初学者比较有用，都是些容易出错误的地方(FPGA some experiences, more useful for beginners, are more vulnerable to the wrong place)

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)