Verilog代码转换到AHB总线APB

实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL

Synopsys® Timing Constraints and Optimization User Guide

Actel双端口存储；通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示)

Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper

vhdl code for carry lookahead addder

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence

在ＦＰＧＡ中产生的频率可调的锯齿波型信号发生器(The frequency of the FPGA to generate the sawtooth waveform signal generator adjustable)

library of protues aaaaaaaa

自己编写的AD7667的数据采集程序，因为之前没用过，首次写！