vhdl

说明：  基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)

数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)

说明：  基于FPGA的OFDM同步，包含时钟模块、ROM读取模块、峰值检测模块、帧同步模块(OFDM synchronization based on FPGA includes clock module, Rom reading module, peak detection module and frame synchronization module)

verilog code for apb to ahb convert

walsh码，在CDMA系统中经常使用到的方法，在quartusII环境下实现的。(walsh code in the CDMA system, the method often used in quartusII environment to achieve.)

vhdl code for register and detemines how register works -vhdl code for register and detemines how register works

Verilog code of SPI configurator for DAC AD7394 and AD7395

说明：  高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)

Thomas课本中的verilog例子。Thomas的verilog在可编程期间领域很有名-Thomas textbook example of verilog. Verilog Thomas in the field during the famous programmable

说明：  ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)