vhdl

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)

just division the clock into 2

说明：  spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

hdb3 using language VHDL(Indoor using VHDL language)

this ebook for electronics hobbiest. VHDL for Beginners

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

这里面有很多的vhdl的编程的源代码，文件是全英文的，例子丰富(That there are a lot of vhdl programming source code, documentation is in English, and examples of rich)

VHDL参考手册，从事FPGA的好帮手，FPGA学院的终身伴侣！-VHDL Reference Manual, in FPGA a good helper, FPGA college life companion!