四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．...

Quartus II软件设计数字电子钟，使用verilog语言编写各个 模块生成symbol files，再用原理图方式制作顶层文件。 完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能； 具有整点报时功能，声响电路发出叫声； (failed to translate)

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of

一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。 数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。 读者还可以通过增加小时的计时功能，实现完整的跑表功能。-A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.

采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化(VHDL hardware description language using the dual-caliber RAM block memory initialization)

关于vhdl的一些例子-on some of the examples of VHDL

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL

本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.