RS232RefComp

基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!

Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of

its the vhdl stuff for ddr sdram controller nice one easily understandable

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

CH341A的I2C接口Labview all vision (CH341A I2C Labview)

通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show

一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference