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1_ADDER
说明: 第1例到第6例的源描述都是从第8例的程序包中
提取出来的,不能单独编译,这些例子的编译与
模拟请参考第8例.(Example No. 1 to the first six cases are the source described in Example 8 from the first package to extract it and can not be a separate compiler, which compiler and simulation examples please refer to the first eight cases.)
- 2008-09-09 18:00:16下载
- 积分:1
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AskPsk
说明: ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)
- 2005-11-26 09:14:32下载
- 积分:1
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SPI串口的内核实现spicore
SPI串口的内核实现spicore
SPI串口的内核实现spicore
SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string
mouth essence to realize spicore the SPI string mouth essence to
realize spicore
- 2023-06-28 18:20:03下载
- 积分:1
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concurrent
VHDL operators basics
- 2013-09-10 14:44:51下载
- 积分:1
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ALU_4bit
4位ALU,有两个4位输入,4位输出实现逻辑运算和算术运算,逻辑与或非,加1,减1等等功能(4 ALU, logical and arithmetic operations)
- 2012-11-18 18:04:59下载
- 积分:1
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8位十进制频率计,通过验证,目标芯片EPF10KLC84
8位十进制频率计,通过验证,目标芯片EPF10KLC84-4-8 decimal Cymometer through authentication, the target chip EPF10KLC84-4
- 2022-07-15 16:44:52下载
- 积分:1
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FPGA2-DSP2-EDMA
例程是基于quartus的,FPGA通过EMIF给DSP发送数据,里面包含了一个简单的状态机和一个基于IP核的fifo,适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
- 2020-12-04 16:09:24下载
- 积分:1
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CODE_VHDL_AUTO COUNTING 0 TO 9(Đếm từ 0 đến 9 hiển thị 1 led 7 đoạn)
- 2022-07-22 09:02:58下载
- 积分:1
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4dbpsk系统的设计实现源码,几个朋友用一个假期的时间协作完成,功能非常好...
4dbpsk系统的设计实现源码,几个朋友用一个假期的时间协作完成,功能非常好-The 4dbpsk system design realization source code, several friends complete it cooperation in one vacation time , the function is extremely good
- 2022-02-04 07:05:28下载
- 积分:1
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cycloneII Quartus verilog to develop a simple sequential circuit
cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
- 2022-03-01 09:19:56下载
- 积分:1