这也是VHDL语言编写的一个小程序，对于VHDL入门很有帮助~~(This is a small program VHDL language, VHDL entry-helpful ~ ~)

sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)

这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作-Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows

counter number one to nine after 1s

常见的几种电机的特征与控制方法-Several common characteristics of the motor and control method

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)