CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)

基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set(Incremental PID FPGA-based design methodology)

DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)

说明：  现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)

VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的.-VHDL state machine design examples, good for the state machine to figure out would be very useful.

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

全数字锁相环的verilog源代码-全数字锁相环的verilog源代码

VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)