FPGA-基于fpga的PWM

三体模型仿真计算样例，基于特定的java浏览器插件对象，以非常形象的方式展示了三体运动物体的规律，可以调节运动参数，实时查看运动变化情况。

说明：  设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

veriloghdl语言熟练的一个很好的cpu代码

《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

此为实现第14.7.9章所需的激励文件 该代码为门级RTL描述。(Stimulus file to verify Section 14.7.9 the functionality of gate vs. RTL description.)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.

Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)