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DDS_DAC_Output
说明: 本工程使用A7系列FPGA产生DDS,用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分:1
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Altera 基础篇公司书籍源码
Altera 基础篇公司书籍源码-Altera Corporation based on chapter books-source
- 2022-10-29 10:20:03下载
- 积分:1
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24,60,100进制的计数器,还有数字时钟,欢迎下载哦~
24,60,100进制的计数器,还有数字时钟,欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~
- 2022-11-11 21:25:03下载
- 积分:1
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SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communicat...
用verilog HDL编写的SPI控制器,从国外网站上找到的。-SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.
- 2023-04-07 12:05:04下载
- 积分:1
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fenpinqi de vhdlchengxu gongnengfnagzhen,政
分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
- 2022-02-21 21:03:34下载
- 积分:1
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频率计
说明: 1、能正确显示输入信号频率;
2、测量频率范围为1Hz ~ 999999Hz;
3、测量结果以十进制数字显示;
4、能测量幅值较小的信号频率;
5、有自动刷新输出数据的功能(如5s刷新一次);
6、有自检模块(如产生100Hz的校准方波);(1. It can correctly display the input signal frequency;
2. The frequency range of measurement is 1Hz ~ 99999hz;
3. The measurement results are displayed in decimal;
4. It can measure signal frequency with small amplitude;
5. It has the function of automatically refreshing the output data (e.g. once in 5S);
6. Self checking module (such as generating 100Hz calibration square wave);)
- 2020-03-28 16:37:56下载
- 积分:1
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实验17 ADC实验
鉴于stm32在keil平台上的ADC采集转化,在LCD屏上显示程序(voltage acquisition adc)
- 2020-06-20 12:40:02下载
- 积分:1
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Simple I2C controller
Simple I2C controller
-- 1) No multimaster
-- 2) No slave mode
-- 3) No fifo s
--
-- notes:
-- Every command is acknowledged. Do not set a new command before previous is acknowledged.
-- Dout is available 1 clock cycle later as cmd_ack
-Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack
- 2023-03-08 10:05:03下载
- 积分:1
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crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,
crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
- 2022-10-07 11:55:03下载
- 积分:1
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它的译码器的VHDL程序
it s vhdl program for decoder
- 2022-11-23 15:15:04下载
- 积分:1