标准的异步串口通讯设计程序――基于VHDL编程

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

说明：  HDMI协议的Verilog实现，通过对RGB三个通道分别进行TMDS编码完成，纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)

多个MATLAB设计滤波器的方法程序以及图形实现(number MATLAB filter design methods and procedures and Graphics)

counter number one to nine after 1s

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)

说明：  Verilog代码实现四分屏，在Vivado平台下实现的，可仿真(Verilog code realizes four screens, which can be simulated under vivado platform)

数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works