VGA采用Spartan 3E板系统的VHDL

TIMING LEARNING -TIMING LEARNING

VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)

使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm

基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir

---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))

thesis for simple virus detection processor which is developed in xilinx

卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve

说明：  此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)

ByteBlasterII 下载线的制作-Download ByteBlasterII production line

VHDL-2008 Just the New Stuff Peter J. Ashenden Consultant Ashenden Designs