ZBT SRAM controller reference design for Xilinx VHDL source code

CAN VHDL Code. Behavioral implementation of CAN bus interface.

it performs the serail dividing operations

synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。(synopsis sv training lab)

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。(Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.)

Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)

滤波器 Generaic FIR Filter(Generaic FIR Filter)

用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

vhdl code for decoder and detemines the basic mechanism of gates of decoder

RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)