ZBT SRAM controller reference design for Xilinx VHDL source code

ＵＣ1698Ｕ驱动160*160ＬＣＤ中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)

在ＦＰＧＡ中产生的频率可调的锯齿波型信号发生器(The frequency of the FPGA to generate the sawtooth waveform signal generator adjustable)

用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

这是altera公司的DE2-35开发板下的一个PS2键盘的源程序代码工程，包括PS2驱动等模块有需要的人，可以下载(Altera DE2-35 development board of the company, the source code of a PS2 keyboard works, including the the PS2 driver modules need, you can download)

用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)

电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti