vhdl code for counterand detemines how counter works

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)

FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

乐曲硬件演奏电路设计的全部VHDL代码，在QuartusII环境下编译通过，已存在QuartusII项目-err

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

adc0809 转换，verilog代码(adc0809 conversion, verilog code)

LVDS De-serialization

一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.