利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。

4 bit ROM for Quartus

很好的quartus软件仿真教程，flash版。-Good quartus software simulation tutorials, flash version.

FFT with FIR created by students in univercity

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.

基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)

代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping

说明：  处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)

用verilog写的很好的cpu core-using Verilog write a good cpu core