-
lic_Xilinx_ISE_Vivado
这是Xilinx ISE 14.X以及vivado、vivado_hls的license,亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
- 2013-04-26 14:51:09下载
- 积分:1
-
UART
实现了UART的底层协议,加入了控制器,其波特率可以根据使用进行调整;发送模块、接收模块相互独立,互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分:1
-
Cordic_matlab
实现自然对数运算的cordic算法的matlab浮点仿真,以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
- 2013-11-01 15:10:09下载
- 积分:1
-
FifoinFIFO
systemc实现的一个fifo,对想要学习systemc的同学很有帮助哦(A fifo systemc achieved, the students want to learn systemc helpful oh)
- 2021-04-18 00:28:52下载
- 积分:1
-
hdb3_codedecode
说明: 用VERILOG实现的,hdb3编码器和解码器,经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)
- 2021-04-22 15:58:49下载
- 积分:1
-
VHDLgoldbook
VHDL黄金参考手册,能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)
- 2013-12-05 16:06:19下载
- 积分:1
-
dianti
实现电梯的相关控制系统,在开发板EGO1上实现,数码管显示相关的楼层和状态(dianti in verilog)
- 2020-12-26 10:59:03下载
- 积分:1
-
nerualnetwork
本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。
(In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)
- 2008-12-14 01:37:03下载
- 积分:1
-
frame_syn
通信系统中数据的传输以帧为单位,在FPGA中帧头检测是通信系统中的一部分,该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)
- 2014-08-27 16:02:54下载
- 积分:1
-
VGA
说明: 用VERILOG编写的一个可以实现VGA显示的程序.....(Prepared using a VERILOG VGA display program can .....)
- 2011-03-04 12:25:21下载
- 积分:1