利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

可以实现DDC各个模块的功能，如内插、抽取、FIR滤波等功能(DDC can realize the function of each module, such as interpolation, extraction, FIR filtering)

一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter

VHDL     贪食蛇游戏用游戏把子上下左右控制蛇的方向，寻找吃的东西，每吃一口就能得到一定的积分，而且蛇的身子会越吃越长，身子越长玩的难度就越大，不能碰墙，不能咬到自己的身体，更不能咬自己的尾巴，等到了一定的分数，就能过关，然后继续玩下一关。

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

this program get 20 point from user and draw functions.

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction