verilog 写的 多功能数字钟

Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack

它工作斯巴达。 使用 xilinx ise 在斯巴达 6e 效果很好

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

可生成rom.初学者可以看看。很不错的。理解后生成rom很容易的。(LPM_ROM .It is good for VHDL new learner)

INTEL 微处理器 第八版 答案 从第二章开始，奇数偶数的答案都有。(INTEL microprocessor eighth edition answer from the beginning of the second chapter, the answer has odd and even.)

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue

Synthetic Aperture Radar (SAR) imaging simulation target, Using wavelet denoising thought, LCMV optimization design array signal processing.

这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

说明：  I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)