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arm7
ARM7 VERILOG源码,非常精简,3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
- 2009-12-02 10:57:51下载
- 积分:1
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Chip_hardware_description_language_related_program
硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)
- 2010-07-28 07:53:40下载
- 积分:1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
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数字频率计毕业论文 不是自己做的
数字频率计毕业论文 不是自己做的-Digital Cymometer thesis do not own. . Ha ha
- 2023-05-02 09:30:02下载
- 积分:1
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实现BCD码的加法,用VHDL实现,是书籍上配套的
实现BCD码的加法,用VHDL实现,是书籍上配套的-BCD ADDER,Using VHDL
- 2022-02-10 02:09:10下载
- 积分:1
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欢迎大家使用该程序,是在FPGA下使用开发的。请大家使用。
欢迎大家使用该程序,是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
- 2022-06-19 03:41:34下载
- 积分:1
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Adder4
本设计是设计了一个4位全加器的内容,是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)
- 2009-05-11 19:50:58下载
- 积分:1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件:
工具:Quartus II 6.0 ,SignalTap II
FPGA:Altera Cyclone EP1C12Q240C8N
SDRAM:HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分:1
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基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用...
基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
- 2022-03-17 09:10:47下载
- 积分:1
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FPGA_PSK
说明: 可以实现2PSK的信号调制,已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分:1