实现BCD码的加法，用VHDL实现，是书籍上配套的

自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过(I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through)

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)

一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8

it performs the serail dividing operations

说明：  该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)

Coding Styles for if Statements and case Statements

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

说明：  misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)