VHDL硬件描述语言与数字逻辑电路设计

基于FPGA的16QAM调制器设计与实现(Design and implementation of 16QAM modulator based on FPGA)

数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)

1．初始状态为4个方向的红灯全亮，时间1秒。 2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。 3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。 4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。 5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。 6．返回2，继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity song is    port(clk_4MHz,clk_4Hz:in std_logic;      ----预置计数器和乐谱产生器的时钟         digit:buffer std_logic_vector(6 downto 0);  ----高、中、低音数码管指示         zero:out std_logic_vector(4 downto 0);     ----用于数码管高位置低  

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!-This book is very important for a designer who wants to design a great digital circuits!

波形产生器：用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure

这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反，这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。  目前所有的都是有效的。

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)