VHDL硬件描述语言与数字逻辑电路设计

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

verilog motor control

FPGA中FLASH配置控制源码,VHDL和Verilog(FPGA source code in the FLASH configuration control, VHDL and Verilog)

vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation

基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar )

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

these files are written in verilog but i am uploading in text format

msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)

DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)