同步FIFO功能，通过Modelsim仿真Verilog语言描述6…

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

说明：  采用FPGA（现场可编程门序列）编写VHDL语言设计多路同步脉冲发生器，对信号进行分频处理，实现四路信号相位相差T/16和T/8的延迟相位输出，实现的四路脉冲与传统的脉冲同步器不同，它具有高集成度，高通用性，容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)

矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境(implement of inverse matrix)

zedboard partial reconfiguration tutorial

用 vhdl 语言实现，上下计数器使用边缘触发一个 4 位纹波计数器。积极的边沿触发。 包含的所有文件。试验台架波形。针对采用赛灵思文件

FPGA与HDMI ADV7511接口源代码(FPGA HDMI Adv7511 interface)

This is a divider, which is depicted as well. It is a programming language Vhdl.

isa总线接口，可以实现与isa总线　的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)