用verilog写的基于cpld的出租车计费器的源码，需要的参考一下

Documentation Of Digital Electronic Systems With VHDL from US DOD.

verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

这是一个vhdl代码的进位选择加法器及其工作100%。

我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

电梯控制器程序设计与仿真的vhdl源代码-Elevator controller design and simulation of vhdl source code

用verilog HDL编写的SPI控制器，从国外网站上找到的。-SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)