更多功能，有文件直接弄到MAX++里运行

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program

用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE

verilog编写的计算百分比模块-Verilog prepared by calculating the percentage module

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

说明：  彩色TFT液晶显示控制电路设计及其ASIC实现(TFT color LCD control circuit design and ASIC realization)

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication

键盘计算器，可实现加减乘数运算 基于fpga nios2(Keyboard, calculator, addition and subtraction can be realized based on fpga nios2 multiplier operator)

本文描述了fpga中的亚稳态时如何产生的，以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。-This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.

介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read