基于Verilog HDL的16位超前进位加法器 分为3个功能子模块

国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)

8051内核的Verilog程序实现，完成普通的单片机8051内核功能.包含综合后文件和测试文件(The 8051 kernel Verilog program complete ordinary microcontroller 8051 kernel function. Contains comprehensive post files and test files)

彩灯控制器 vhdl语言开发 eda实验-Lantern controller vhdl language test eda

硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.

8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)

cic设计 verilog verilog(cic verilog design verilog)

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文(LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps Thesis)