基于Verilog HDL的16位超前进位加法器 分为3个功能子模块

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

ALTERA FPGA CLPD

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

一个基于FPGA的串口程序,已经经过验证,对用FPGA做串口的朋友提供参考和借鉴!-an FPGA-based serial procedures have proven, right Serial do with FPGA reference for a friend and borrow!

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)

移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents

this come from alter ,you can look and find it on line about jtag.

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)