基于Verilog HDL的16位超前进位加法器 分为3个功能子模块

Bringing SMW2:YI Back To LIFE Through Rom!

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

说明：  FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。(FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.)

说明：  基于HSPICE实现的反相器链，并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example

用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)

该文件用在CPLD上的，和C语言很接近，5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.

可供初学者学习 比较简单 一读就能明白 LED7数码显示程序(Relatively simple for beginners to learn the first reading of the digital display program will be able to understand LED7)

基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)

利用VHDL语言编写的一个16分频器，另外可以在程序中修改为任意2N的分频器-use VHDL prepared a 16 dividers, Also in the revision process to be arbitrary 2 N Divider