ping

Control with DAC conversion

bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)

说明：  适合入门及进阶的100个VHDL练习题，从易到难(100 VHDL exercises for beginners and advanced students, from easy to difficult)

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

xlinx sparten 3E实验板，实现时钟闹钟功能，闹钟播放电子音乐，时钟，闹钟通过LCD屏显示。自己写的，亲测可用。                                                                                                                    

各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8(CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8 )

quartus工具入门文档，altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.

AHDL语言介绍，很详细的介绍AHDL语言介绍，很详细的介绍(AHDL language introduction, a detailed explanation)

该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)