Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.

握手程序，可以完美实现跨时钟域的数据传输(handshake and testbench，verilog HDL)

自适应均衡器

小家电常用芯片HT66F0185的UART 使用例子，已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)

数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

高斯最小频移键控（Gaussian Filtered Minimum Shift Keying），这是GSM系统采用的调制方式。数字调制解调技术是数字蜂窝移动通信系统空中接口的重要组成部分。GMSK调制是在MSK（最小频移键控）调制器之前插入高斯低通预调制滤波器这样一种调制方式。GMSK提高了数字移动通信的频谱利用率和通信质量。(Gauss Filtered Minimum Shift Keying is a modulation method used in GSM system. Digital modem technology is an important part of air interface of digital cellular mobile communication system. GMSK modulation is a method of inserting a Gaussian low-pass pre-modulation filter before the MSK (minimum frequency shift keying) modulator. GMSK improves the spectrum utilization and communication quality of digital mobile communication.)

基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； (Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The phase adjustable sine wave, square wave duty ratio is adjustable )