Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

BCD to 7 segments display decoder

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

说明：  verilog语言书写，单周期CPU源码(single period CPU)

FPGA实现DSP的Verilog 示例(FPGA realization of DSP-Verilog Example)

SAP-1硬件描述语言（使用Verilog语言）

thesis about design and implementation neural network using FPGA

altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience

主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data