Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

HDLC接口协议的FPGA实现使用verilog-design of HDLC

this is fpga based vhdl coding and report for wavlet based image compression in vhdl

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.

rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)

加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)

Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)

用Verilog实现的呼吸灯，用Verilog实现的呼吸灯(Verilog huxideng)

支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU，verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)