Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

说明：  Verilog学习文档，介绍基本知识点，语言要素(for learning Verilog)

键盘输入串口输出显示字符,通过串口显示键盘输入的字符-Keyboard input serial output display characters, the keyboard input through serial display characters

原理图和程序，都已经调试好了！可以直接使用！

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

verilog编写的DAC2902程序，用于高速的数模转换(verilog language,using for DAC2902 digital analog converter)

This source is used to control 7 segments on FPGA boad

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

Vhdl实用教程，可帮助初学者迅速掌握VHDL的编写-Vhdl practical tutorials to help beginners to grasp quickly the preparation of VHDL

ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)