100例VHDL语言解释，北京理工大学毕业…

making a simple clock using altera vhdl

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

fifi asyncronous and syncronus

VLSI based question set

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)

说明：  32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考(32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only)

用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

SVPWM脉冲的产生。