计数器的 vhdl 代码

RD1006--I2C与存储器的IP 代码及说明文档，lattice提供，I2C Controller for Serial EEPROMs 源代码可用，并且包含tb文件-RD1006-- I2C and memory IP code and documentation. Lattice offer I2C Controller for Serial EEPROMs source code available, and document contains tb-

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top

以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。-VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function.

基于FPGA的多电平载波移相SPWM方法实现(theCarried-Phase-shift SPWM method of Multi-Level converter based on FPGA)

本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

当时是用于课程设计而编写的代码，经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）

基于vhdl的dds任意函数发生器的实现和仿真

这是脉冲宽度调制技术的VHDL代码，包括一个比较器，正弦波发生器，锯齿波发生器，脉冲宽度调制器等。