FPGA驱动DM9000

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)

完成RS（5，3）编码程序，运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)

说明：  基于IIC协议的EEPROM模型，可实现串行数据转并行数据，并行数据转串行数据，分为EEPROM模块，EEPROM_WR模块，signal模块，Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)

AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23)

说明：  学习vhdl硬件描述语言的一些例子的原代码(VHDL hardware description language to learn some examples of the original code)

this project is about FIR FIlter By VHdl codes in the ISE.

说明：  这个是64bit矩阵乘法实现代码，语言是verilog。(This is the 64 bit matrix multiplication implementation code, and the language is Verilog.)

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)