SDRAM猝发读写Verilog程序

并行前缀加法器（也被称为carrytree

基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)

本文介绍了 8 位Vedic乘法器提升传播执行延迟，当相比传统的乘数，像阵列乘法器、 布劳恩乘数、 改性的 booth  型乘法器和华莱士树型乘法器

其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例(Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD)

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )

最大值求解是利用System Generator平台实现的比较方便不用自己写verilog代码就可以在Xilinx平台下使用，非常方便实用！

本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。(This book briefly introduces the Verilog hardware description language basics, including basic elements of language and basic structure, and the use of the language at various levels on the digital system modeling. The book lists a large number of examples to help readers master the language itself and the modeling of the actual digital system design is also helpful. Verilog HDL book is a primer for a computer, electronic, electrical and automatic control and other specialized courses related to materials, but also for the researchers as a reference.)

基于单片机显示原理的IO和LED显示原理(Based on the principle of IO chip and LED display shows the principle)

利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)